ISE报错" Warning:There is an 'U'|'X'|'W'|'Z'|'-' in an arithme
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ISE报错" Warning:There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,the result will be 'X
程序如下,仿真的时候提示" Warning:There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,the result will be 'X'(es).".
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity kilometers is
Port ( RESET :in STD_LOGIC;
CLKOUT :in STD_LOGIC;
KM_CNT0 :out STD_LOGIC_VECTOR (3 downto 0);
KM_CNT1 :out STD_LOGIC_VECTOR (3 downto 0);
KM_CNT2 :out STD_LOGIC_VECTOR (3 downto 0);
KM_CNT3 :out STD_LOGIC_VECTOR (3 downto 0));
end kilometers;
architecture Behavioral of kilometers is
SIGNAL CNT0:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CNT1:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CNT2:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CNT3:STD_LOGIC_VECTOR(3 DOWNTO 0);
begin
PROCESS(RESET,CLKOUT)
BEGIN
IF RESET='1'
THEN CNT0
程序如下,仿真的时候提示" Warning:There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,the result will be 'X'(es).".
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity kilometers is
Port ( RESET :in STD_LOGIC;
CLKOUT :in STD_LOGIC;
KM_CNT0 :out STD_LOGIC_VECTOR (3 downto 0);
KM_CNT1 :out STD_LOGIC_VECTOR (3 downto 0);
KM_CNT2 :out STD_LOGIC_VECTOR (3 downto 0);
KM_CNT3 :out STD_LOGIC_VECTOR (3 downto 0));
end kilometers;
architecture Behavioral of kilometers is
SIGNAL CNT0:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CNT1:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CNT2:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CNT3:STD_LOGIC_VECTOR(3 DOWNTO 0);
begin
PROCESS(RESET,CLKOUT)
BEGIN
IF RESET='1'
THEN CNT0
仿真时是要赋初值的问题.
例如在architecture上面,component定义下面直接写上
signal CLKOUT : STD_LOGIC:=‘0’; 这样就行
例如在architecture上面,component定义下面直接写上
signal CLKOUT : STD_LOGIC:=‘0’; 这样就行
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